| Keynote lecture |
| "Trends and Perspectives in deepsubmicron circuit design" |
Since the 60's the computing power of Integrated circuits (ICs) have been growing exponentially: every 18 months the number of transistors on an IC is doubled. This growth is known as "Moores law" and this law has even become a self-fulfilling prophecy meanwhile. This is because many parties - from clean room equipment manufacturers on the start of the innovation chain, up to IC designers at the end of the innovation chain - need to make plans. They all use Moore's law which is more formally dictated by the SIA (Semiconductor Industry Association) roadmap. Every new technology generation has smaller feature sizes and thus more transistors per area. Today an IC may contain up to 14 Million transistors per square centimeter operating up to 1.5 GHz clock frequency. Thanks to this downscaling in combination with mass production, the cost per transistor is decreasing exponentially over the generations. The dominating IC technology is CMOS and the driving applications of ICs are all digital: like PCs, (wireless) digital communication equipment, cameras etc.
Technically the downscaling is more complex: Until around 1998 this downscaling has yielded mainly chip size reduction and speed improvement, but since that time the scaling yields mainly improved power efficiency for digital circuits. This is because since that time the supply voltage is almost decreasing linearly with the feature size, which hardly the case before 1998. For digital circuits but especially for analog circuits this gives rise to new challenges.
Challenges in the digital domain are: leakage currents during standby, crosstalk between wires, substrate bounce, and timing in high-speed databusses. For analog circuits the main challenge is the low supply voltage, which soon will be below 1 Volt. Around these supply voltages it's impossible to use conventional circuit techniques, and new topologies have to be invented. The new analog topologies make use of digital computing power, which is now available at low cost. It's a challenge to shift the analog problems to the digital domain, where they can easier solved today.
If Moore's law continues, it's for sure a challenge for IC-designers to design appropriate circuits. But if Moore's law ever may stop, e.g. for economic reasons, than the only way companies can distinguish themselves is through better design. So in both scenarios deep-submicron IC design is an important challenge.
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prof. dr. ir. Bram Nauta
B.Nauta@utwente.nl
Electrical Engineering
EL/TN, 3242
P.O. Box 217
7500 AE Enschede
The Netherlands
Phone +31 53 489 2655
Secretary +31 53 489 2644
Fax +31 53 489 1034 |
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Bram Nauta was born in Hengelo, The Netherlands, in 1964. In 1987 he received the M.Sc degree (cum laude) in electrical engineering from the University of Twente, Enschede, The Netherlands. In 1991 he received the Ph.D. degree from the same university on the subject of analog CMOS filters for very high frequencies.
In 1991 he joined the Mixed-Signal Circuits and Systems Department of Philips Research, Eindhoven the Netherlands, where he worked on high speed AD converters. From 1994 he led a research group in the same department, working on "analog key modules". In 1998 he returned to the University of Twente, as full professor heading the IC Design group in the MESA+ Research Institute and department of Electrical Engineering (http://icd.el.utwente.nl). His current research interest is analog CMOS circuits for transceivers. Besides, he is also part-time consultant at Philips Research Laboratories.
His Ph.D. thesis was published as a book: Analog CMOS Filters for Very High Frequencies, Boston, MA, Kluwer, 1993. He holds 8 patents in circuit design and he received the "Shell Study Tour Award" for his Ph.D. Work. From 1997-1999 he served as Associate Editor of IEEE Transactions on Circuits and Systems -II; Analog and Digital Signal Processing, and in 1998 he served as Guest Editor for IEEE Journal of Solid-State Circuits. In 2001 he became Associate Editor for IEEE Journal of Solid-State Circuits.
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| Keynote lecture |
| "Monolithic CMOS Pixel Detectors for Radiation Imaging" |
Monolithic CMOS Pixel Detectors constitute a novel technique for silicon position sensitive detectors. The sensors are fabricated in a standard CMOS process used for modern ICs manufacturing. Their development derives benefit from a visible light CMOS camera, emerged in a last decade as a competitor to standard CCDs having well established position in this domain. The key element is a use of an silicon epitaxial layer of usually 2-15 µm thickness grown on a highly doped silicon as a sensitive detector volume. The charge generated by the impinging particle is collected mainly through thermal diffusion within a typical time of hundred of nanoseconds by n-well implantation diodes. The active volume is underneath the readout electronics, allowing 100% fill factor. The baseline pixel circuitry for particle detection and for visible light cameras is identical, and comprises only 3 MOS transistors and a diode collecting the charge. The first prototype structures named MIMOSA-s were fabricated and their functionality has been successfully tested. The measured tracking performance of minimum ionising particles includes spatial resolution of 1.5 µm and detection efficiency close to 100%, resulting from a high SNR of more than 30. Tests show that CMOS Pixel Detectors are able to withstand an integrated electromagnetic radiation of a few hundred kRad and the neutron fluence close to 1012 n/cm2. These optimistic results motivate further studies driven by highly demanding performances of the vertex detector foreseen at the future linear collider and other applications like particle beam monitoring, imaging of radioactively marked samples, dosimetry of radioactive sources, etc. The research work is oriented on three main axes: design of a large, wafer scale devices comprising arrays of several millions of pixels, radiation hardness studies including improvements through layout hardening and investigation towards integration of the complete detecting system on a single chip.
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Wojciech Dulinski
Laboratoire d'Electronique et de Physique des Systèmes Instrumentaux
EA 3425
23, Rue du Loess - Boîte Postale 20
F-67037 Strasbourg Cedex 02
FRANCE
Tel. +33 3 90 24 28 68
Fax. +33 3 90 24 28 70
dulinski@lepsi.in2p3.fr
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Wojciech Dulinski obtained his PhD from the Jagiellonian University, Cracow, Poland in 1985 on the development of 3-D position sensitive multiwire gas detectors for Cherenkov Ring Imaging systems for particle physics experiments. He used his knowledge in this field working as a post-doc at Institute of Nuclear Physics at Strasbourg, France, where he designed Barrel RICH MWPC-s for DELPHI Collaboration. Since 1989 he become a staff member of a newly created LEPSI laboratory and he concentrated his work on the application of various solid state radiation detectors. He participated in RD20 collaboration developing silicon sensors for LHC experiments and he is still a member of RD49 collaboration working with CVD diamond particle trackers.
Since 1999 his main field of research is the development of Monolithic Pixel Sensors for charged particle tracking and imaging. He is a co-inventor of this novel detection technique and he participated in all phases of the work leading to the demonstration of its usefulness. This includes the device design using standard VLSI methodology, development of specific test equipment and active participation in all measurements. He is a member of an R&D group designing specific CMOS sensors for a vertex detector at a future linear collider experiment. He is also the scientific co-ordinator of LEPSI team working for a medical imaging applications of this devices within EU grant founded SUCIMA Collaboration.
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