Session 4: High Density Interconnect Technology

Keynote lecture
"Multilayer thin film technology, solving high-density interconnect and assembly problems"
When looking at the evolution of electronic circuits from a chip interconnection and packaging perspective, we observe a growing gap between the evolution of VLSI technology and that of packaging and interconnection technology. The rate of change in the packaging industry significantly lags behind that of the IC industry. About ten years ago, thin film multi-chip modules were proposed as a solution for the increasing wiring demands of IC-circuits. Due to economic constraints and the adaptability of the competing, more established, printed circuit board and ceramic technologies, this has not happened until now. The competing technologies were able to push their capabilities to new limits and solve the majority of interconnect problems. With the new generations of IC technologies, this is likely to change. When considering the IC technology roadmaps, one can observe that the IC complexity grows faster than the integration capabilities of the new technologies. An almost inevitable result of this is an increase in chip area and an increase in chip pin count, following the so-called Rent's rule. Within a few years, this will result in IC's with peripheral wire bond pads at a pitch of only 40 mm. Even using flip chip interconnects, distributed across the chip surface, very tight pad pitches will result. A 100 pin count die will have a full area array flip chip pitch of about 100 mm, a 900 pin count die will still require a full array of 300 mm pitch. This goes beyond the traditional laminate and ceramic technologies, which seem to be limited to minimum pitches of 100 mm. Thin film multilayer technology, based on aluminium and copper interconnect lines, combined with photosensitive dielectric layers offer a solution to these problems. Line widths and spacings in the order of 10 mm can be achieved cost effectively using conventional mask processing on 200 mm diameter wafers or even large area substrates. If possible, the overall module size should however be kept below 3x3cm for yield reasons. Some will argue that systems will be integrated fully on a single die, System-on-a-Chip COC, thus requiring only limited interconnects. Technological limitations, system diversity and economic reality point towards a different direction, the so-called System-In-a-Package SIP approach. As integration of functions becomes more successful, electronic (sub)systems will become smaller and more attractive to build as a single module. The interconnecting substrate will combine the role of high density IC interconnect as well as the interconnection of the module and the rest of the system. For this latter task, the module will "translate" the very high density interconnects at die level to the much coarser pitch of the printed circuit boards. This is similar to the "interposer" substrate in a ball grid array (BGA) package. An ideal thin film technology should therefore be realised on a laminate substrate base. An example of such an MCM-SL/D technology will be presented. Thin film technology also enables the high density integration of high quality passive circuit elements, such as resistors, capacitors, inductors and various types of transmission lines. This is particularly of interest for high frequency devices that require many of these elements. IMEC's approach to heterogeneous microwave integration will be discussed and examples of realised circuits will be shown. Given the small contact pitch of die and the increasing operating frequencies, flip chip assembly of die will become more important. The fine pitch flip chip bumping technologies use thin film technology for the realisation of "redistribution"-layers and for the electroplating of the solder bumps.
Eric Beyne IMEC Kapeldreef 75 B-3001 Leuven Belgium Tel : +32 (0)16 281 261 Fax : +32(0)16 281 501 beyne@imec.be
Eric Beyne was born on May 26, 1960 in Tienen, Belgium. He obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the University of Leuven. From 1983 till 1985, he was a research assistant at this University. In 1986, he joined IMEC, where he worked on his Ph.D. on the interconnection of high-frequency digital circuits. He is presently head of the high-density interconnection and packaging group at IMEC. The research in this group is focused on multilayer thin film interconnect technologies, system-in-a-package integration, rf-integration and wafer level packaging techniques. This research group with over 30 people, from 9 different countries, performs research with national and international industry. Eric Beyne is secretary of the IMAPS-Benelux committee and member of the IMAPS-Europe technical program committee. IMAPS is the international microelectronics and packaging society.